1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device which is provided on a chip to protect an internal circuit from electro-static discharge, and more particularly to a silicon controlled Rectifier type) SCR-type ESD protection device to achieve high-speed turn-on operation.
2. Description of the Related Art
The recent complex and high density design of semiconductor devices is bringing about such a problem that semiconductor devices are damaged by electrostatic discharge (ESD) during an assembling process or the like in the fabrication process. As one measure against the problem, an on-chip electrostatic discharge protection device (hereinafter also called “ESD protection device”), which protects elements in an internal circuit by efficiently discharging an electrostatic discharge current in a safe path, is provided in the chip of a semiconductor device. Especially, a CMOS transistor is sensitive remarkably to the electro-static discharge, because a gate oxide film is very thin so that the breakdown voltage of the gate oxide film decreased. In other words, the difference between a breakdown voltage of the gate oxide film and a trigger voltage, namely a voltage that the electro-static discharge protection device begins to become low impedance, becomes small. Therefore, there is a high possibility that a voltage above a permissive level is applied to the gate oxide film and the internal circuit is destroyed, when a great deal of currents flow. Thus, it is required for the recent electro-static discharge protection device to decrease the trigger voltage as the breakdown voltage of the gate oxide film has decreased.
Generally, an input circuit of a CMOS transistor circuit for a high-speed operation needs short RC delay and the RC delay should be short even if the ESD protection is added. Thus, a protection resistance element with a large resistance value cannot be used while it is widely used. Also, it is required that a layout area of the protection device is small from the viewpoint of manufacturing cost in addition of capacity delay.
An SCR, which can satisfy the above requests, is generally used as an ESD protection device because the SCR has the excellent advantages of a low capacity, a very low holding voltage and a small layout area, compared with other protection devices. The SCR-type ESD protection device is disclosed in U.S. Pat. Nos. 5,225,702, 5,465,189 and 5,502,317 (first to third conventional examples) and “A low-voltage triggering SCR (silicon controlled rectifier) for on-chip ESD protection ato output and input pads”, (IEEE electron Device Letters, Vol. 12, the No. 1, pp. 21-22, January 1991) (fourth conventional example) by Chatterjee A. et al.
FIG. 1 is a plan view showing the layout of a low voltage trigger SCR in the ESD protection device of the first conventional example, and FIG. 2 is a cross sectional view of the ESD protection device of FIG. 1 along the A-A line. As shown in FIGS. 1 and 2, in the ESD protection device of the first conventional example, a first P-well 3a and an N-well 2 and a second P-well 3b are formed in the surface of a P+ semiconductor substrate 1. A P+ region 4 functioning as an anode of the SCR and a N+ region 5 functioning as an N-well pick-up region thereof are formed in the regions of the N-well 2 partitioned by the device separation isolation regions 6. A pair of the N+ regions 9 is formed for the source and drain of a NMOS transistor in the P-well 3b adjacent to the N-well 2. A gate electrode 8 is formed above the substrate between the N+ regions 9. Also, of the N+ regions 9 of the NMOS transistor, a drain region (the N+ region 9 on the side of the P+ region 4) is connected with the N-well 2, and the source region (the N+ region 9 on the opposite side) functions as the cathode of the SCR.
An input pad together with the N+ region 5 as the N-well pick-up region is connected with the P+ region 4 in the N-well 2, and the N+ region 5 as the N-well pick-up region is connected with a power supply potential Vdd. Also, a ground pad is connected with the N+ region 9 functioning as the cathode of the SCR. It should be noted that the reference numeral 7 denotes a latch-up prevention P+ region, and is grounded and functions as a guard ring. In the figure, only a part of the guard ring is shown.
When a positive electro-static over voltage is applied to the input pad connected with the SCR, avalanche breakdown occurs in the PN junction of the side of the drain of the NMOS transistor, and the MOS transistor begins to generate electron-hole pars. As a result, the substrate current, that is the hole current, flows toward the P+ guard ring, and the substrate potential, that is the local electric potential near the device, rises. For this reason, the electric potential at the bottom of the cathode of the SCR, i.e., the source of the NMOS transistor rises and the N+/P-well diode is biased in a forward direction so that the lateral-type NPN (L-NPN) bipolar device 11 is set to a conductive state. Also, the current flows through the N-well 2 to generate the potential difference in the N-well 2. When the potential at the bottom of the anode of the SCR, i.e., the P+ region 4 in the N-well 2 decreases lower than the potential of the N+ region 5 as the N-well pick-up region, and the P+/N-well diode is biased in a forward direction. Thus, a vertical-type PNP (V-PNP) bipolar device 12 turns on.
Because the V-PNP bipolar device 12 supplies current toward the substrate, which is then fed back to the base of the L-NPN transistor 11, thereby amplifying the base current of the L-NPN transistor. Therefore, the SCR is set to the operation state within a time of less than one nano second. This forms a low-resistance current path between the anode (the P+ region 4) and the cathode (the N+ region 9).
The SCR of the first conventional example is called a low voltage trigger SCR (LVTSCR), but besides, various types of SCRs to be described below exist and those characteristics are shown in FIG. 7.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 09-107074: a fifth conventional example) discloses an ESD protection integrated circuit using a substrate trigger L-NPN transistor.
FIG. 3 is a plan view showing a layout of the ESD protection device of the fifth conventional example, and FIG. 4 is a cross sectional view of the ESD protection device along the B-B line of FIG. 3. In this ESD protection device, a P+ region 10 as a trigger tap is provided directly in the second P-well 3b instead of the NMOS transistor. The substrate potential rises through a triggering current supplied from the P+ region 10. In this conventional example, an N-type MOSFET is used as a circuit for supplying a substrate current, and a circuit connecting the source and the P+ region functions as a substrate bias circuit.
In addition to these conventional examples. U.S. Laid Open Patent Application (2003/0075726: sixth conventional example), Japanese Laid Open Patent Application (JP-P2003-203985A: seventh conventional example), U.S. Pat. No. 5,225,702 (eighth conventional example) are known as the method for supplying the current to the N-well as for the trigger method of the SCR.
Moreover, as shown in FIG. 10, in the sixth conventional example, triggering taps are arranged between the anode and the cathode, and currents are supplied to the respective trigger electrodes to achieve a high-speed trigger operation. This is called as a double trigger-SCR.
In the seventh conventional example, as shown in FIG. 9, a trigger device is connected with a diode between the anode 4 and the N-well pick-up region 5 in the N-well. When the trigger device is turned on, a current flow through the diode in the N-well and then the V-PNP bipolar transistor is turned to trigger the SCR. This type of SCR is called as a V-PNP triggered SCR.
Main concern in the industry about using SCRs as ESD protection devices is unintentional latch-up during normal operating conditions, that is, an uncontrolled triggering of SCR during normal operation, such as the system noise. One method to avoid latch-up risk in the SCR ESD protection devices is to adjust the holding voltage to keep above the supply voltage, including some safety margin. Such SCRs are described in U.S. Pat. Nos. 5,012,317 (ninth conventional example) and 4,939,616 (tenth conventional example), and in (2002/0153571: eleventh conventional example).
As shown in FIG. 8, resistance elements are added to the substrate or an N-well to increase the holding voltage. However, in order to make it possible to adjust the holding voltage by the external resistance elements, it is necessary to decrease the N-well resistance and the P-well resistance of the SCR structure sufficiently in this circuit structure. However, this is also difficult in the SCR which uses a high resistance substrate and/or STI(shallow trench isolation). In view of this point, a layout in which the P-well effective resistance and the N-well effective resistance can be decreased is described in the eleventh conventional example and in “High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune for IC Operation”, (Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2002 (1A.3.1): twelfth conventional example) by Marcus P. J. Mergens, and Christian C. Russ, et.al, and U.S. Patent Publication (2003/0218841; thirteenth conventional example), which was filed by the inventors of the present invention.
FIG. 5 is a plan view showing a layout of SCR described in the tenth conventional example (This SCR is called as HHI-SCR (High Holding Current-SCR). FIG. 6A is a cross sectional view of the SCR along the C-C line of FIG. 5, and FIG. 6B is a cross sectional view of the SCR along the D-D line of FIG. 5. As shown in FIGS. 5, 6A and 6B, each of the anode and the cathode of the SCR is divided into a plurality of regions and an N-well voltage control N+ region and a P-well voltage control P+ region are inserted between the regions. A triggering current is supplied to the P+ region between the cathode regions. FIG. 11 shows a cross sectional view of the SCR corrected to a usual layout to describe a circuit operation. The resistance element of 2 to 10 Ω is connected between the P-well voltage control P+ region and the ground potential. The N-well resistance is controlled by changing the external resistance element value, and the number of connections between the N-well voltage control N+ region s in the N-well and the input terminals. The holding voltage can be adjusted through the control of the N-well resistance. While the SCR carries out the trigger operation, the triggering current is supplied to the parallel circuit of the resistance element, and the PN diode (containing P-well resistance) between the P-well voltage control P+ region and the cathode. Because the resistance value of the PN diode is very high generally, a clamp voltage is determined based on the resistance element between the P-well voltage control P+ region and the ground potential. This resistance value is set previously to a low value. These facts would be understood from FIG. 7 showing the characteristic of the SCR.
In this SCR, an NMOS is used as the trigger device. The trigger device discharges a current until the SCR becomes low resistance, and the I-V characteristic is similar to that of the NMOS. Therefore, both of the triggering current and the holding current are set to a very higher value of 100 to 500 mA in the holding voltage adjustable SCR than the usual SCR. As shown in FIG. 12, in the tenth conventional example, two trigger devices are connected with the N-well voltage control N+ region and the P-well voltage control P+ region, respectively. The triggering current is supplied to each of resistance elements from the corresponding trigger circuit to trigger the SCR at two points.
However, there are problems as shown below in the above-mentioned conventional examples.
The conventional SCR type ESD protection device in the conventional examples 1 to 7 has the following problems. As the miniaturization of the CMOS-LSIs gain pace so the gate oxide film needs to become thinner. This lowers the breakdown voltage of the gate oxide film so that the gate oxide film is very susceptible to ESD. As reported by J. Wu et al. in “Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, p. 287-295, for example, the conventional system called a low-voltage trigger SCR takes time for the SCR to have a low resistance after it is turned on. This results in the overshooting of the voltage before the SCR is turned on, in which case the internal circuit may not be protected. The conventional examples 1 to 7 employ larger spacing between the anode and the cathode to adjust the holding voltage to an acceptable voltage, resulting in facing a severe problem of voltage overshooting.
In a process using a high resistance substrate, the triggering current is as very low as 1 to a few ten mA, and the triggering voltage is almost not affected even if the resistance value of the trigger device or a path through which the triggering current flows is high. However, because the holding voltage is as very low as about 1 V, there is a risk that the SCR is latched up through the usual operation. Therefore, such an SCR may be applicable only if diodes are connected in series to increase the total holding voltage.
In an SCR using a low resistance substrate, the distance between anode and the cathode is made wide to increase the holding voltage or a special layout is used like the tenth and eleventh conventional examples. In the SCR with the holding voltage set high, the triggering current necessarily increases greatly in case of use of the conventional methods. In this case, the triggering current is in a range of 100 mA to 1 A typically. Surge current is discharged through the trigger device until the SCR is turned on. When the resistance value of the current path is high, there is a possibility that the triggering voltage becomes very high, so that the protected circuit cannot be protected because of over-voltage, as shown in FIG. 7. For example, in the SCR described in the first to fourth conventional examples, the resistance of the current path through which the triggering current flows, e.g., the resistance of the P+/N-well diode cannot be decreased in many cases under the restraint of the layout.
However, this resistance value becomes a problem actually. In a method employed in the tenth eleventh conventional example, and in the twelfth conventional example, the trigger current is shunted by the external resistance element, as low as 2 ohm, to lower the triggering voltage.
Also, considering from the viewpoint of the trigger operation, it is necessary from the efficiency to bias the PN diode near the opposite region of the anode and the cathode in a forward direction in order to trigger the SCR efficiently, as pointed out by the above two conventional examples. However, because the current of the P+/N-well diode flows on the opposite side to the anode and the cathode, a region where the P+/N-well diode is biased in the forward direction is localized, resulting in low trigger efficiency. It should be noted that because it is not possible to decrease the N-well resistance, it is not preferable from the viewpoint of the holding voltage control, in the method in which the triggering current is supplied to the N-well, such as the sixth and seventh conventional examples.
As described above, conventionally, there is no ESD protection device capable of meeting the structure in which the vertical-type bipolar transistor device 12 of the SCR is turned on at high speed, the structure in which the substrate current can be supplied efficiently, and the structure in which the layout area can be decreased. The development of the ESD protection device which can meet the above requests is strongly demanded.
Also, as described above, it is very important to adjust the holding voltage of the SCR stably. Especially, in recent years, the STI (Shallow Trench Isolation) process has been used and the resistances in the wells have a large deviation. In actual, the N-well resistance and the substrate resistance often depend on the N+ region area in the N-well, the P+ region area in the P-well and the layout of them. When the SCR is applied to the product, it is necessary to tailor the performance such as the holding voltage through experimental production and the evaluation.
In the SCR, in which the trigger device is not used like the eighth and ninth conventional examples, the triggering voltage is 40 V and in the modified SCR (MSCR), the triggering voltage is 10 V However, because the breakdown voltage of a fine element or device at present is considerably lower than the above value, the SCRs are not applicable.
In the holding voltage adjustable SCR (, which is also called HHI-SCR) of a double trigger system shown in FIG. 12, in which the trigger operation is carried out by the different trigger devices, as described in the tenth conventional example, the timings when the trigger devices begin to supply the triggering current are not matched to each other. Therefore, when the current flows into the N-well, the hole current outputted from the PN diode flows into the P-well voltage control P+ region. However, because the resistance value of the P-well voltage control P+ region is generally set low, the triggering current has become high. Also, in the holding voltage adjusting method of the tenth conventional example, the degrees of freedom of the design is low because the triggering voltage and the holding voltage are adjusted using the same resistance elements.
In addition, U.S. Patent Publication (2003/0164508: fourteenth conventional example) is a modification of LVTSCR, using a triggering voltage adapter network and a holding voltage adapter network In order to change the characteristic of current vs. voltage by adjusting the triggering voltage and the holding voltage of the SCR to meet the special requirement of various chips.
However, LVTSCR itself has several problems, such as voltage overshooting, as is described above. This conventional example is substantially the same as the well-known ggMOS (gate-coupled MOS). Also, in U.S. Patent Publication (2003/0213971: fifteenth conventional example), it is described in the specification of this reference that this structure is employed in order to increase a current amplification factor β of each of the bipolar transistors. However, our experimental production suggested that there is a case where a base resistance of each bipolar transistor in the SCR is remarkably low, when an N+ region in an N-well and P+ region in a P-well are connected directly to a pad and a ground potential. Therefore, the SCR would not operate in the worst.